The present application relates generally to the manufacture of semiconductor devices, and more specifically to the formation of isolation regions between adjacent devices, and particularly between adjacent devices that perform different functions or are positioned on different electrical nets.
A trend in the development of semiconductor manufacturing technologies has been to increase the density of devices per chip, and hence decrease the areal dimensions associated with each device. This trend applies not only to the structures formed in device regions per se, but also to inter-device structures such as isolation structures between active regions, which can occupy a relatively large area of a device or chip.
A number of techniques are known for providing isolation between adjacent devices. In a process using shallow trench isolation (STI), for example, active regions are typically defined in a semiconductor substrate and device isolation regions are then etched into the semiconductor substrate to form trenches that are backfilled with a dielectric material. However, such a process is limited by lithographic dimensions, which place a lower limit on both the trench width and the associated device-to-device spacing, i.e., pitch.